CACTI 5.3
Normal Interface RAM Size (bytes)
Detailed Interface Nr. of Banks
Pure RAM Interface Read/Write Ports
FAQ Read Ports
Write Ports
Single Ended Read Ports
Nr. of Bits Read Out
Technology Node (nm)
Temperature (300-400 K, steps of 10)
RAM cell/transistor type in data array
(choose ITRS transistor for SRAM cell)
ITRS-HP ITRS-LSTP ITRS-LOP LP-DRAM COMM-DRAM
Peripheral and global circuitry transistor
type in data array
ITRS-HP ITRS-LSTP ITRS-LOP
RAM cell/transistor type in tag array
(choose ITRS transistor for SRAM cell)
ITRS-HP ITRS-LSTP ITRS-LOP LP-DRAM COMM-DRAM
Peripheral and global circuitry transistor
type in tag array
ITRS-HP ITRS-LSTP ITRS-LOP
Interconnect projection type Aggressive Conservative
Type of wire outside mat Semi-global Global