CACTI 5.3
Normal Interface Cache Size (bytes)
Detailed Interface Line Size (bytes)
Pure RAM Interface Associativity
FAQ Nr. of Banks
Technology Node (nm)
Read/Write Ports
Read Ports
Write Ports
Single Ended Read Ports
Nr. of Bits Read Out
Change Tag No Yes
Nr. of Bits per Tag
Type of Cache Normal Serial Fast
Temperature (300-400 K, steps of 10)
RAM cell/transistor type in data array
(choose ITRS transistor for SRAM cell)
ITRS-HP ITRS-LSTP ITRS-LOP LP-DRAM COMM-DRAM
Peripheral and global circuitry transistor
type in data array
ITRS-HP ITRS-LSTP ITRS-LOP
RAM cell/transistor type in tag array
(choose ITRS transistor for SRAM cell)
ITRS-HP ITRS-LSTP ITRS-LOP LP-DRAM COMM-DRAM
Peripheral and global circuitry transistor
type in tag array
ITRS-HP ITRS-LSTP ITRS-LOP
Interconnect projection type Aggressive Conservative
Type of wire outside mat Semi-global Global